Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
| RXRDYCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| TXRDYCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| TXIDLECLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| DELTACTSCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| TXDISINTCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| OVERRUNCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| DELTARXBRKCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| STARTCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| FRAMERRCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| PARITYERRCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RXNOISECLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| ABERRCLR | Writing 1 clears the corresponding bit in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |